The architecture of the entity(not_gate) is defined by “architecture notLogic of not_gate is”. The architecture name is given as “ andLogic”. Once the entity is declared, the next step is to define the architecture of the entity (not_gate). The entity is declared as not_gate and A is declared as input, Y is declared as Output. The NOT gate symbol and NOT gate truth table is shown below. If you want to know the basics like what is NOT gate and how it works, you can check out the link for our previous tutorial. The above values of A,B,Y corresponds to the Truth Table of the AND Gate. Now that all the input combinations for A and B(00,01,10,11) are forced to the input signals, move the cursor throughout the waveform graph from 0ps to 400ps. The values of A,B,Y at corresponding time intervals are given below.
#Modelsim force code
The above code is compiled, simulated with different input values as shown below. The architecture is terminated by “end andLogic” The Boolean operator ‘AND’ is used to perform the AND operation between A and B. Now that we know Y is the output, we know that output is nothing but the AND operation of the two inputs A and B. The architecture of the entity(and_gate) is defined by “architecture andLogic of andd_ Gaate is”. Once the entity is declared, the next step is to define the architecture of the entity ( andd_ Gaate). The entity is decalred as andd_ Gaate and A,B are decalred as inputs, Y is decalred as Output. The AND gate symbol and AND gate truth table are shown below. If you want to know the basics like what is AND gate and how it works, you can check out the link for our previous tutorial.
#Modelsim force how to
Learners are encouraged to learn how to compile, force the input values, simulate as these steps won't be repeated in the forthcoming tutorials. This is how the VHDL logic gate codes are written, compiled, and simulated. The above values of A, B, Y corresponds to the Truth Table of the OR Gate. The values of A, B, Y at corresponding time intervals are given below. Move the cursor throughout the waveform graph from 0ps to 500ps. Now that all the input combinations for A and B (00,01,10,11) are forced to the input signals. Similarly, the other four input combinations are given and their outputs are verified as shown below.įrom the waveform graph, the output Y changes according to the given Inputs A and B. Now, we can see that for A=0, B=0, Y=0, which verifies with Truth Table of OR Gate. There is a yellow colour cursor on the waveform, move the cursor so that the corresponding inputs and outputs are shown. Click the run icon, we can see the waveforms on the graph for 100 ps. There is a Run icon in the toolbar near the timer as shown below. Step 9: Now that the inputs are given, let's Run the simulation. Set the Value to 0 for A and similarly for B set the value 0 and click OK. A menu pops up from that choose “Force” option. Step 7: Now, let us simulate the circuit by giving the inputs. Step 6: The waveform window opens with declared inputs and outputs on the right side of the window as shown below. Right Click on the entity name (OR_gate) and click Add Wave as shown below. Click Work Here, we can see our entity name (OR_gate). Step 4: Once you select Start Simulation, a dialog box opens, and there is a folder called “Work”. On the ToolBar, there is an option called ”Simulate” as shown below. Now that the compilation is successful. Let's simulate the designed circuit. Step 3: If you find a red mark or unsuccessful please check your code if it has errors. The files are compiled and we can see a green tick mark “ü” and “Compile of entity name. To understand the general structure of the VHDL code, please refer to the first tutorial. Now that we know the Truth Table, let's start scripting the VHDL code for OR Gate. If you want to know the basics like what is or gate and how it works, you can check out the link for our previous tutorial. The Boolean function and Truth Table of the OR gate are given below. Let us start designing the basic logic gates using VHDL. Double click the OR_gate.vhd, an editor will open up on the right side of the window. Step 7: Now that the file is added, we can start scripting our first VHDL program.
Step 6: The project will be created and the file OR_gate will be added as shown below. Here, for example, the file name is given as OR_gate.
Give a file name and choose the file type as VHDL and click OK. Step 5: ' Create a new project file' opens up. Step 4: The project will be created and the “Add Items to the project” dialog box opens. For example, the project name given below is “basic_ logicgates” Enter the name for your project and click OK as shown below. Step 3: The create new project dialog box opens up.